1. Technical Field
The present invention relates to a current output control device, a current output control method, a digitally controlled oscillator, a digital PLL, a frequency synthesizer, a digital FLL and a semiconductor device that control an output current value according to change in an input code. For instance, the present invention relates to a current output control device, a current output control method, a digitally controlled oscillator, a digital PLL, a frequency synthesizer, a digital FLL and a semiconductor device that are suitable for operating at high precision in response to change in an input code.
2. Related Art
Recently, digital PLL circuits with digitalized control signals of Phase Locked Loop (PLL) circuits are being employed in electronic devices such as mobile phones, communication devices and personal computers. Digital PLL circuits replace analogue circuits with digital circuits, and accordingly due to advances in processors enable space savings to be achieved and power savings to be made.
For example, a clock signal controlled by PLL is employed as a system clock signal of a microprocessor. Advances are being made in lower power consumption (lower current consumption) of microcontrollers (referred to below as microcomputers) equipped with microprocessors. There are accordingly more occasions in which microcomputers are operated intermittently. When such intermittent operation is performed using an analogue PLL, the charge of a charge amplifier is discharged whenever the PLL is switched OFF, and capacity needs to be charged from zero when the PLL is switched back ON, with this impeding power consumption reduction.
There are descriptions related to digital PLLs in, for example, Japanese Patent Application Laid-Open (JP-A) No. 2002-335155 (Patent Document 1) and JP-A No. 2011-205339 (Patent Document 2). Patent Documents 1 and 2 describe All Digital PLLs (ADPLLs) in which all of the control signals of the PLL circuit are digitalized.
In such an ADPLL there is also a large difference to previous analogue PLLs in relation to the control method of the oscillation circuit. Namely, in an analogue PLL, a Voltage Controlled Oscillator (VCO) is employed in which the oscillation frequency is determined by the voltage level of capacity charged by charge of an amount of phase difference to a reference clock. However in an ADPLL, generally a Digitally controlled Oscillator (DCO) is employed in which the oscillation frequency is determined by an input value of a digital code.
In an ADPLL, switching of the oscillation frequency of the Digitally controlled Oscillator (DCO) is performed by switching the code input to the DCO. Such input code switching is performed based on a specific clock.
The oscillation frequency of the DCO accordingly fluctuates when a glitch (intermittent noise) occurs due to a fluctuation in clock frequency when input code switching, with a resulting deterioration in jitter characteristics (frequency stability).
For example, in Patent Document 1, an IDAC is employed to change an output current value to change the frequency of a current control oscillation circuit. Specifically, an IDAC configured as illustrated in FIG. 7 is employed, and the oscillation frequency is changed by controlling current of a ring oscillation circuit that has each transistor connected to a current mirror circuit by switching transistors that are weighted at 2 to the power n.
In such a circuit configuration, when a code for oscillation frequency switching is input to each of the transistors weighted by transistor channel width (W)/channel length (L) and connection number, a glitch that occurs due to differences in propagation speed of each bit and due to differences in switch timing is also input.
As a result, there are sometimes occasions when a transistor is selected that is not the transistor that should have been selected. In such cases an abnormal current value is output, and the oscillation frequency of the ring oscillation circuit using this current value becomes unstable, with this being a cause of deterioration in jitter characteristics in the ring oscillation circuit.
Note that it is conceivable to use capacitance to remove glitches occurring when digital values are switched, however due to the need to add new capacitance this is not desirable from the perspectives of decreasing circuit size and lowering cost.
Moreover, Patent Document 2 is directed towards solving a problem when performing frequency control using a Binary control method in a DCO, namely to solving the problem that noise from switching readily occurs due to the influence of mismatches in parasitic capacitance and transistor characteristics at the point of change of the most significant bit. Technology is described for controlling oscillation frequency by splitting an 8 bit oscillator control word OTW [7:0] split into its upper 5 bits and lower 3 bits, and converting the upper 5 bits into an OTWb [7:3] for performing Binary control, and converting the lower 3 bits into an OTWu [13:0] for performing Unary control.
However, in the technology of Patent Document 2, glitches occurring at the time the input code input to the DCO changes when switching the oscillation frequency of the DCO cannot be avoided, and sometimes the oscillation frequency of the DCO becomes unstable.